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| (R) EL4584 Data Sheet July 25, 2005 FN7174.2 Horizontal Genlock, 4FSC The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it. The reference signal is a horizontal sync signal, TTL/CMOS format, which can be easily derived from an analog composite video signal with the EL4583 Sync Separator. An input signal to "coast" is provided for applications were periodic disturbances are present in the reference video timing such as VTR head switching. The Lock detector output indicates correct lock. The divider ratio is four ratios for NTSC and four similar ratios for the PAL video timing standards, by external selection of three control pins. These four ratios have been selected for common video applications including 4FSC, 3FSC, 13.5MHz (CCIR 601 format) and square picture elements used in some workstation graphics. To generate 8FSC, 6FSC, 27MHz (CCIR 601 format) etc. use the EL4585, which includes an additional divide-by-two stage. For applications where these frequencies are inappropriate or for general purpose PLL applications the internal divider can be bypassed and an external divider chain used. FREQUENCIES AND DIVISORS FUNCTION Divisor PAL FOSC (MHz) Divisor NTSC FOSC MHz) NOTES: 1. 3FSC numbers do not yield integer divisors. 2. CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL. 3. Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion. 3FSC CCIR 601 (NOTE 1) (NOTE 2) 851 13.301 682 10.738 864 13.5 858 13.5 SQUARE (NOTE 3) 944 14.75 780 12.273 4FSC 1135 17.734 910 14.318 Features * 36MHz, general purpose PLL * 4FSC based timing (use the EL4585 for 8FSC) * Compatible with EL4583 sync separator * VCXO, Xtal, or LC tank oscillator * < 2ns jitter (VCXO) * User controlled PLL capture and lock * Compatible with NTSC and PAL TV formats * 8 pre-programmed TV scan rate clock divisors * Selectable external divide for custom ratios * Single 5V, low current operation * Pb-Free plus anneal available (RoHS compliant) Applications * Pixel clock regeneration * Video compression engine (MPEG) clock generator * Video capture or digitization * PIP (Picture in Picture) timing generator * Text or graphics overlay timing Ordering Information PART NUMBER EL4584CN EL4584CS EL4584CS-T7 EL4584CS-T13 EL4584CSZ (See Note) EL4584CSZ-T7 (See Note) PACKAGE 16-Pin PDIP 16-Pin SO (0.150") 16-Pin SO (0.150") 16-Pin SO (0.150") 16-Pin SO (0.150") (Pb-free) 16-Pin SO (0.150") (Pb-free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 EL4584CSZ-T13 16-Pin SO (0.150") (See Note) (Pb-free) *For 6FSC and 8FSC clock frequencies, see EL4585 datasheet. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Demo Board A demo PCB is available for this product. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.2003-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL4584 Pinout EL4584 (16-PIN SO, PDIP) TOP VIEW 2 FN7174.2 July 25, 2005 EL4584 Absolute Maximum Ratings (TA = 25C) VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36MHz Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER IDD VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current IIH Input High Current IIL Input Low Current IIH Input High Current VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage IOL Output Low Current IOH Output High Current IOL/IOH Current Ratio ILEAK Filter Out NOTE: 1. All inputs to 0V, COAST floating. VDD = 5V, TA = 25C unless otherwise noted CONDITIONS MIN TYP 2 MAX 4 1.5 3.5 UNIT mA V V nA 100 -100 -60 60 100 0.4 2.4 0.4 2.4 0.4 2.4 200 300 -300 1.05 -100 1.0 1 -200 0.95 100 nA nA A A V V V V V V A A VDD = 5V (Note 1) All inputs except COAST, VIN = 1.5V All inputs except COAST, VIN = 3.5V COAST pin, VIN = 1.5V COAST pin, VIN = 3.5V Lock Det, IOL = 1.6mA Lock Det, IOH = -1.6mA CLK, IOL = 3.2mA CLK, IOH = -3.2mA OSC Out, IOL = 200A OSC Out, IOH = -200A Filter Out, VOUT = 2.5V Filter Out, VOUT = 2.5V Filter Out, VOUT = 2.5V Coast Mode, VDD > VOUT > 0V -100 AC Electrical Specifications PARAMETER VCO Gain @ 20MHz HSYNC S/N Ratio Jitter Jitter NOTE: VDD = 5V, TA = 25C unless otherwise noted CONDITIONS MIN TYP 15.5 35 1 10 MAX UNIT dB dB ns ns Test circuit 1 VDD = 5V (Note 1) VCXO oscillator LC oscillator (Typ) 1. Noisy video signal input to EL4583, HSYNC input to EL4584. Test for positive signal lock. 3 FN7174.2 July 25, 2005 EL4584 Pin Descriptions PIN NUMBER 1, 2, 16 3 4 5 6 7 PIN NAME PROG A,B,C OSC/VCO OUT VDD (A) OSC/VCO IN VSS (A) CHARGE PUMP OUT FUNCTION Digital inputs to select / N value for internal counter. See table below for values. Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit. Analog positive supply for oscillator, PLL circuits. Input from external VCO. Analog ground for oscillator, PLL circuits. Connect to loop filter. If the HSYNC phase is leading or HSYNC frequency > CLK / N, current is pumped into the filter capacitor to increase VCO frequency. If HSYNC phase is lagging or frequency < CLK / N, current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when locked, charge pump goes to a high impedance state. Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting CLK / N. When low, the internal divider is disabled and EXT DIV is an input from an external / N. Tri-state logic input. Low (<1/3*VCC) = normal mode, Hi Z (or 1/3 to 2/3*VCC) = fast lock mode, High (>2/3*VCC) = coast mode. Horizontal sync pulse (CMOS level) input. Positive supply for digital, I/O circuits. Lock Detect output. Low level when PLL is locked. Pulses high when out of lock. External Divide input when DIV SEL is low, internal /N output when DIV SEL is high. Ground for digital, I/O circuits. Buffered output of the VCO. 8 9 10 11 12 13 14 15 DIV SELECT COAST HSYNC IN VDD (D) LOCK DET EXT DIV VSS (D) CLK OUT TABLE 1. VCO DIVISORS PROG A (PIN 16) 0 0 0 0 1 1 1 1 PROG B (PIN 1) 0 0 1 1 0 0 1 1 PROG C (PIN 2) 0 1 0 1 0 1 0 1 DIV VALUE (N) 851 864 944 1135 682 858 780 910 4 FN7174.2 July 25, 2005 EL4584 Timing Diagrams Falling edge of HSYNC + 110ns locks to rising edge of Ext Div signal. FIGURE 1. PLL LOCKED CONDITION (PHASE ERROR = 0) E = (T/TH) x 360 TH = HSYNC period T = phase error period FIGURE 2. OUT OF LOCK CONDITION FIGURE 3. TEST CIRCUIT 1 5 FN7174.2 July 25, 2005 EL4584 Typical Performance Curves IDD vs FOSC EL4584 OSC GAIN @ 20MHz vs TEMPERATURE TYPICAL VARACTOR OSC GAIN vs FOSC CHARGE PUMP DUTY CYCLE vs E Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 1.8 1.6 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 1.23W 1.2 1 0.91W 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SO16 (0.150") JA=110C/W PDIP16 JA=81C/W 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1.43W 1.25W PDIP16 JA=70C/W SO16 (0.150") JA=80C/W 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (C) 6 FN7174.2 July 25, 2005 EL4584 Block Diagram Description Of Operation The horizontal sync signal (CMOS level, falling leading edge) is input to HSYNC input (pin 10). This signal is delayed about 110ns, the falling edge of which becomes the reference to which the clock output will be locked. (See timing diagrams.) The clock is generated by the signal on pin 5, OSC in. There are 2 general types of VCO that can be used with the EL4584, LC and crystal controlled. Additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be purchased with everything inside a metal can. The modules are very forgiving of PCB layout, but cost more than discrete solutions. The VCO or VCXO is used to generate the clock. An LC tank resonator has greater "pull" than a crystal controlled circuit, but will also be more likely to drift over time, and thus will generate more jitter. The "pullability" of the circuit refers to the ability to "pull" the frequency of oscillation away from its center frequency by modulating the voltage on the control pin of a VCO module or varactor, and is a function of the slope and range of the capacitancevoltage curve of the varactor or VCO module used. The VCO signal is sent to a divide by N counter, and to the CLK out pin. The divisor N is determined by the state of pins 1,2, and 16 and is described in table 1 above. The divided signal is sent, along with the delayed Hsync input, to the phase/frequency detector, which compares the two signals for phase and frequency differences. Any phase difference is converted to a current at the charge pump output FILTER (pin 7). A VCO with positive frequency deviation with control voltage must be used. Varactors have negative capacitance slope with voltage, resulting in positive frequency deviation with control voltage for the oscillators in figures 10 and 11. modules are already tuned to the desired frequency, so this step is not necessary if using one of these units. The range of the charge pump output (pin 7) is 0 to 5 volts and it can source or sink a maximum of about 300A, so all frequency control must be accomplished with variable capacitance from the varactor within this range. Crystal oscillators are more stable than LC oscillators, which translates into lower jitter, but LC oscillators can be pulled from their mid-point values further, resulting in a greater capture and locking range. If the incoming horizontal sync signal is known to be very stable, then a crystal oscillator circuit can be used. If the HSYNC signal experiences frequency variations of greater than about 300ppm, an LC oscillator should be considered, as crystal oscillators are very difficult to pull this far. When HSYNC input frequency is greater than CLK frequency / N, charge pump output (pin 7) sources current into the filter capacitor, increasing the voltage across the varactor, which lowers its capacitance, thus tending to increase VCO frequency. Conversely, filter output pulls current from the filter capacitor when HSYNC frequency is less than CLK / N, forcing the VCO frequency lower. Loop Filter The loop filter controls how fast the VCO will respond to a change in filter output stimulus. Its components should be chosen so that fast lock can be achieved, yet with a minimum of VCO "hunting", preferably in one to two oscillations of charge pump output, assuming the VCO frequency starts within capture range. If the filter is underdamped, the VCO will over and under-shoot the desired operating point many times before a stable lock takes place. It is possible to under-damp the filter so much that the loop itself oscillates, and VCO lock is never achieved. If the filter is over-damped, the VCO response time will be excessive and many cycles will be required for a lock condition. Overdamping is also characterized by an easily unlocked system because the filter can't respond fast enough to perturbations in VCO frequency. A severely over damped system will seem to endlessly oscillate, like a very large mass at the end FN7174.2 July 25, 2005 VCO The VCO should be tuned so its frequency of oscillation is very close to the required clock output frequency when the voltage on the varactor is 2.5 volts. VCXO and VCO 7 EL4584 of a long pendulum. Due to parasitic effects of PCB traces and component variables, it will take some trial and error experimentation to determine the best values to use for any given situation. Use the component tables as a starting point, but be aware that deviation from these values is not out of the ordinary. possible. VCO frequency will drift as charge leaks from the filter capacitor, and the voltage changes the VCO operating point. Coast mode is intended to be used when noise or signal degradation result in loss of horizontal sync for many cycles. The phase detector will not attempt to adjust to the resultant loss of signal so that when horizontal sync returns, sync lock can be re-established quickly. However, if much VCO drift has occurred, it may take as long to re-lock as when restarting. External Divide DIV SEL (pin 8) controls the use of the internal divider. When high, the internal divider is enabled and EXT DIV (pin 13) outputs the CLK out divided by N. This is the signal to which the horizontal sync input will lock. When divide select is low, the internal divider output is disabled, and external divide becomes an input from an external divider, so that a divisor other than one of the 8 pre-programmed internal divisors can be used. Lock Detect Lock detect (pin 12) will go low when lock is established. Any DC current path from charge pump out will skew EXT DIV relative to HSYNC in, tending to offset or add to the 110ns internal delay, depending on which way the extra current is flowing. This offset is called static phase error, and is always present in any PLL system. If, when the part stabilizes in a locked mode, lock detect is not low, adding or subtracting from the loop filter series resistor R2 will change this static phase error to allow LDET to go low while in lock. The goal is to put the rising edge of EXT DIV in sync with the falling edge of HSYNC + 110ns. (See timing diagrams.) Increasing R2 decreases phase error, while decreasing R2 increases phase error. (Phase error is positive when EXT DIV lags HSYNC.) The resistance needed will depend on VCO design or VCXO module selection. Normal Mode Normal mode is enabled by pulling COAST (pin 9) low (below 1/3*VCC). If HSYNC and CLK / N have any phase or frequency difference, an error signal is generated and sent to the charge pump. The charge pump will either force current into or out of the filter capacitor in an attempt to modulate the VCO frequency. Modulation will continue until the phase and frequency of CLK / N exactly match the HSYNC input. When the phase and frequency match (with some offset in phase that is a function of the VCO characteristics), the error signal goes to zero, lock detect no longer pulses high, and the charge pump enters a high impedance state. The clock is now locked to the HSYNC input. As long as phase and frequency differences remain small, the PLL can adjust the VCO to remain locked and lock detect remains low. Applications Information Choosing External Components 1. To choose LC VCO components, first pick the desired operating frequency. For our example we will use 14.31818MHz, with an HSYNC frequency of 15.734kHz. 2. Choose a reasonable inductor value (10-20H works well). We choose 15H. 3. Calculate CT needed to produce FOSC. 1 F OSC = ---------------------2 LC T 1 1 C T = -------------------- = --------------------------------------------------------------------- = 8.2pF 22 2 2 4 ( 14.318e6 ) ( 15e - 6 ) 4 F L Fast Lock Mode Fast Lock mode is enabled by either allowing coast to float, or pulling it to mid supply (between 1/3 and 2/3*VCC). In this mode, lock is achieved much faster than in normal mode, but the clock divisor is modified on the fly to achieve this. If the phase detector detects an error of enough magnitude, the clock is either inhibited or reset to attempt a "fast" lock of the signals. Forcing the clock to be synchronized to the HSYNC input this way allows a lock in approximately 2 H-cycles, but the clock spacing will not be regular during this time. Once the near lock condition is attained, charge pump output should be very close to its lock-on value and placing the device into normal mode should result in a normal lock very quickly. Fast Lock mode is intended to be used where HSYNC becomes irregular, until a stable signal is again obtained. 4. From the varactor data sheet find CV @ 2.5V, the desired lock voltage. CV = 23pF for our SMV1204-12, for example. 5. C2 should be about 10CV, so we choose C2 = 220pF for our example. 6. Calculate C1. Since: C1 C2 CV C T = --------------------------------------------------------------------------( C 1 C 2 ) + ( C 1 C V ) + ( C 2 C V ) Coast Mode Coast mode is enabled by pulling COAST (pin 9) high (above 2/3*VCC). In coast mode the internal phase detector is disabled and filter out remains in high impedance mode to keep filter out voltage and VCO frequency as constant a then: C2 CT CV C 1 = ------------------------------------------------------------------------( C2 CV ) -( C2 CT ) - ( CT CV ) 8 FN7174.2 July 25, 2005 EL4584 For our example, C1 = 14pF. (A trim cap may be used for fine tuning.) Examples for each frequency using the internal divider follow. XTAL VCO COMPONENT VALUES (APPROXIMATE) FREQUENCY (MHz) 13.301 13.5 14.75 17.734 10.738 12.273 14.318 R1 (k) 300 300 300 300 300 300 300 C1 (pF) 15 15 15 15 15 15 15 C2 (F) 0.001 0.001 0.001 0.001 0.001 0.001 0.001 Typical Application Horizontal genlock provides clock for an analog to digital converter, digitizing analog video. The above oscillators are arranged as Colpitts oscillators, and the structure is redrawn here to emphasize the split capacitance used in a Colpitts oscillator. It should be noted that this oscillator configuration is just one of literally hundreds possible, and the configuration shown here does not necessarily represent the best solution for all applications. Crystal manufacturers are very informative sources on the design and use of oscillators in a wide variety of applications, and the reader is encouraged to become familiar with them. FIGURE 4. TYPICAL LC VCO LC VCO COMPONENT VALUES (APPROXIMATE) (NOTE) FREQUENCY (MHZ) 13.301 13.5 14.75 17.734 10.738 12.273 14.318 L1 (H) 15 15 12 12 22 18 15 C1 (pF) 18 17 18 10 20 17 14 C2 (pF) 220 220 220 220 220 220 220 FIGURE 6. COLPITTS OSCILLATOR NOTE: Use shielded inductors for optimum performance. C1 is to adjust the center frequency, C2 DC isolates the control from the oscillator, and V1 is the primary control device. C2 should be much larger than CV so that V1 has maximum modulation capability. The frequency of oscillation is given by: 1 F = ------------------------12 LCT C1 C2 CV C T = ------------------------------------------------------------------------( C1 C2 ) + ( C1 CV ) + ( C2 CV ) Choosing Loop Filter Components The PLL, VCO, and loop filter can be described as: FIGURE 5. TYPICAL XTAL VCO 9 FN7174.2 July 25, 2005 EL4584 Where: Kd = phase detector gain in A/rad F(s) = loop filter impedance in V/A KVCO = VCO gain in rad/s/V N = internal or external divisor It can be shown that for the loop filter shown below: C3 K d K VCO 2N n C 3 = -----------------------, C 4 = ------ , R 3 = ----------------------2 10 K d K VCO N n K d K VCO ( 4.77e - 5 ) ( 6.05e6 ) C 3 = ----------------------- = ----------------------------------------------------- = 0.01F 2 2 ( 910 ) ( 5000 ) N n C3 C 4 = ------ = 0.0001F 10 2N n ( 2 ) ( 910 ) ( 1 ) ( 5000 ) R 3 = ----------------------- = ----------------------------------------------------- = 31.5k ( 4.77e - 5 ) ( 6.05e6 ) K d K VCO Where n = loop filter bandwidth, and = loop filter damping factor. 1. Kd = 300A/2rad = 4.77e-5A/rad for the EL4584. 2. The loop bandwidth should be about HSYNC frequency/20, and the damping ratio should be 1 for optimum performance. For our example, n = 15.734kHz/20 = 787Hz5000rad/S. 3. N = 910 from table 1. VCOfrequency 14.31818M N = ---------------------------------------------------------- = ----------------------------- = 910 H - SYNCfrequency 15.73426k increases, T decreases. For LDET to be low at lock, |T| < 50 ns. C4 is used mainly to attenuate high frequency noise from the charge pump. Lock Time Let = R3C3. As T increases, damping increases, but so does lock time. Decreasing T decreases damping and speeds up loop response, but increases overshoot and thus increases the number of hunting oscillations before lock. Critical damping ( = 1) occurs at minimum lock time. Because decreased damping also decreases loop stability, it is sometimes desirable to design slightly overdamped ( > 1), trading lock time for increased stability. 4. KVCO represents how much the VCO frequency changes for each volt applied at the control pin. It is assumed (but probably is not) linear about the lock point (2.5V). Its value depends on the VCO configuration and the varactor transfer function CV = F(VC), where VC is the reverse bias control voltage, and CV is varactor capacitance. Since F(VC) is nonlinear, it is probably best to build the VCO and measure KVCO about 2.5V. The results of one such measurement are shown below. The slope of the curve is determined by linear regression techniques and equals KVCO. For our example, KVCO = 6.05 Mrad/S/V. FOSC vs VC, LC VCO FIGURE 7. TYPICAL LOOP FILTER LC LOOP FILTER COMPONENTS (APPROXIMATE) FREQUENCY (MHZ) 13.301 13.5 14.75 17.734 10.738 R2 (k) 100 100 100 100 100 100 100 R3 (k) 30 30 33 39 22 27 30 C3 (F) 0.01 0.01 0.01 0.01 0.01 0.01 0.01 C4 (F) 0.001 0.001 0.001 0.001 0.001 0.001 0.001 5. Now we can solve for C3, C4, and R3. We choose R3 = 30k for convenience. 6. Notice R2 has little effect on the loop filter design. R2 should be large, around 100k, and can be adjusted to compensate for any static phase error T at lock, but if made too large, will slow loop response. If R2 is made smaller, T (see timing diagrams) increases, and if R2 10 12.273 14.318 FN7174.2 July 25, 2005 EL4584 XTAL LOOP FILTER COMPONENTS (APPROXIMATE) FREQUENCY (MHz) 13.301 13.5 14.75 17.734 10.738 12.273 14.318 R2 (k) 100 100 100 100 100 100 100 R3 (M) 4.3 4.3 4.3 4.3 4.3 4.3 4.3 C3 (pF) 68 68 68 68 68 68 68 C4 (pF) 6.8 6.8 6.8 6.8 6.8 6.8 6.8 PCB Layout Considerations It is highly recommended that power and ground planes be used in layout. The oscillator and filter sections constitute a feedback loop and thus care must be taken to avoid any feedback signal influencing the oscillator except at the control input. The entire oscillator/filter section should be surrounded by copper ground to prevent unwanted influences from nearby signals. Use separate paths for analog and digital supplies, keeping the analog (oscillator section) as short and free from spurious signals as possible. Careful attention must be paid to correct bypassing. Keep lead lengths short and place bypass caps as close to the supply pins as possible. If laying out a PCB to use discrete components for the VCO section, care must be taken to avoid parasitic capacitance at the OSC pins 3 and 5, and FILTER out (pin 7). Remove ground and power plane copper above and below these traces to avoid making a capacitive connection to them. It is also recommended to enclose the oscillator section within a shielded cage to reduce external influences on the VCO, as they tend to be very sensitive to "handwaving" influences, the LC variety being more sensitive than crystal controlled oscillators. In general, the higher the operating frequency, the more important these considerations are. Self contained VCXO or VCO modules are already mounted in a shielding cage and therefore do not require as much consideration in layout. Many crystal manufacturers publish informative literature regarding use and layout of oscillators which should be helpful. Demo Board 11 FN7174.2 July 25, 2005 EL4584 The VCO and loop filter section of the EL4583/4/5 demo board can be implemented in the following configurations: (1) VCXO (2) XTAL (3) LC TANK Component Sources Inductors * Dale Electronics E. Highway 50 PO Box 180 Yankton, SD 57078-0180 (605) 665-9301 El Monte, CA 91731 (818) 443-2121 Varactors * Sky Works Solutions Inc. 20 Sylvan Road Woburn, MA 01801 (781) 376-3000 www.skyworksinc.com * Motorola Semiconductor Products 2100 E. Elliot Tempe, AZ 85284 (602) 244-6900 Note: These sources are provided for information purposes only. No endorsement of these companies is implied by this listing. Crystals, VCXO, VCO Modules * Connor-Winfield 2111 Comprehensive Drive Aurora, IL 60606 (708) 851-4722 * Piezo Systems 100 K Street PO Box 619 Carlisle, PA 17013 (717) 249-2151 * Reeves-Hoffman 400 West North Street Carlisle, PA 17013 (717) 243-5929 * SaRonix 151 Laura Lane Palo Alto, CA 94043 (415) 856-6900 * Standard Crystal 9940 Baldwin Place All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7174.2 July 25, 2005 |
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